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MC74AC377, MC74ACT377 Octal D Flip-Flop with Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
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PDIP-20 N SUFFIX CASE 738 1
* * * * * * * * * * * *
Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETs or 73 Gates Pb-Free Packages are Available
SOIC-20W DW SUFFIX CASE 751D 1
TSSOP-20 DT SUFFIX CASE 948E 1
VCC 20
O7 19
D7 18
D6 17
O6 16
O5 15
D5 14
D4 13
O4 12
CP 11 1
SOEIAJ-20 M SUFFIX CASE 967
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
1 CE
2 O0
3 D0
4 D1
5 O1
6 O2
7 D2
8 D3
9 O3
10 GND
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 7 of this data sheet.
Figure 1. Pinout: 20-Lead Packages Conductors
(Top View)
PIN NAMES
PIN D0-D7 CE Q0-Q7 CP FUNCTION Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input
D0 D1 D2 D3 D4 D5 D6 D7 CP CE O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
(c) Semiconductor Components Industries, LLC, 2006
1
December, 2006 - Rev. 9
Publication Order Number: MC74AC377/D
MC74AC377, MC74ACT377
MODE SELECT-FUNCTION TABLE
Inputs Operating Mode Load 1 Load 0 Hold (Do Nothing)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
Outputs Dn H L X X Qn H L No Change No Change
CP
CE L L H
X
H
D0 CE
D1
D2
D3
D4
D5
D6
D7
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
CP O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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MC74AC377, MC74ACT377
MAXIMUM RATINGS
Symbol VCC Vin Vout Iin Iout ICC Tstg qJA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Thermal Resistance, (Junction-to-Ambient) SOIC TSSOP PDIP Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) VCC = 5.5 V; TA = 125C (Note 4) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 97 129 69 > 2000 > 200 > 1000 > 100 Unit V V V mA mA mA C C/W
VESD
ESD Withstand Voltage
V
ILatchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 5) AC Devices except Schmitt Inputs Input Rise and Fall Time (Note 6) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current - High Output Current - Low VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 - - - - - - -40 - - Typ 5.0 5.0 - 150 40 25 10 8.0 - 25 - - Max 6.0 5.5 VCC - - - - - 140 85 -24 24 ns/V C C mA mA ns/V V V Unit
5. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 6. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74AC377, MC74ACT377
74AC - DC CHARACTERISTICS
Symbol VIH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current Maximum Input Leakage Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 TA = +25C Typ 1.50 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 - TA = -40C to +85C Unit V V V V V V V V V V V V V V V V V V mA mA mA mA Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 mA
Guaranteed Limits 2.10 3.15 3.85 0.90 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 - 8.0 2.10 3.15 3.85 0.90 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 80
VIL
VOH
*VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 mA
0.002 0.001 0.001 -
*VIN = VIL or VIH -12 mA -24 mA IOH -24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
- - -
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
74AC - AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6.
Symbol Parameter VCC* (V) 3.3 5.0 CP to Qn CP to Qn 3.3 5.0 3.3 5.0 TA = +25C CL = 50 pF Min 90 140 3.0 2.0 3.5 2.5 Typ - - - Max - 13.0 9.0 13.0 10.0 TA = -40C to +85C CL = 50 pF Min 75 125 1.5 1.5 2.0 1.5 Max - 14.0 10.0 14.5 11.0 MHz ns ns Unit
fmax tPLH tPHL
Maximum Clock Frequency Propagation Delay Propagation Delay
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
74AC - AC OPERATING REQUIREMENTS
Symbol ts th ts th tw Parameter Setup Time, HIGH or LOW Hold Time, HIGH or LOW Setup Time, HIGH or LOW Hold Time, HIGH or LOW CP Pulse Width Dn to CP Dn to CP CE to CP CE to CP HIGH or LOW VCC* (V) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 TA = +25C CL = 50 pF Typ - - - - - 5.5 4.07 0 1.0 6.0 4.0 0 1.0 5.5 4.0 TA = -40C to +85C 6.0 4.5 0 1.0 7.5 4.5 0 1.0 6.0 4.5 Guaranteed Minimum Unit ns ns ns ns
ns
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC377, MC74ACT377
74ACT - DC CHARACTERISTICS
Symbol VIH Parameter Minimum High Level Input Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN DICCT IOLD IOHD ICC Maximum Input Leakage Current Additional Max ICC/Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 TA = +255C Typ 1.5 1.5 1.5 1.5 4.49 5.49 - 0.001 0.001 - - 0.6 - - TA = -405C to +855C Unit Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 mA *VIN = VIL or VIH -24 mA IOH -24 mA IOUT = 50 mA *VIN = VIL or VIH -24 mA IOH -24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 - - 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 80 V
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V V V V mA mA mA
5.5
8.0
mA
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
74ACT - AC CHARACTERISTICS For Figures and Waveforms -- See Figures 4, 5, and 6.
Symbol fmax tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay Propagation Delay CP to Qn CP to Qn VCC* (V) 5.0 5.0 5.0 TA = +25C CL = 50 pF Min 140 3.0 3.5 Typ - - - Max - 9.0 10 TA = -40C to +85C CL = 50 pF Min 125 2.5 2.5 Max - 10 11 MHz ns ns Unit
*Voltage Range 5.0 V is 5.0 V 0.5 V.
74ACT - AC OPERATING REQUIREMENTS
Symbol ts th ts th tw Parameter Setup Time, HIGH or LOW Hold Time, HIGH or LOW Setup Time, HIGH or LOW Hold Time, HIGH or LOW CP Pulse Width Dn to CP Dn to CP CE to CP CE to CP VCC* (V) 5.0 5.0 5.0 5.0 5.0 TA = +25C CL = 50 pF Typ - - - - - TA = -40C to +85C CL = 50 pF Unit ns ns ns ns ns
Guaranteed Minimum 4.5 1.0 4.5 1.0 4.0 5.5 1.0 5.5 1.0 4.5
HIGH or LOW
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Value Typ 4.5 90 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
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MC74AC377, MC74ACT377
SWITCHING WAVEFORMS
tr CLOCK 50% tw 1/fmax tPLH Q 50%
tf VCC GND CE 50% tsu tPHL CLOCK th VCC 50% GND VCC
Figure 4.
Figure 5.
VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND
Figure 6.
450 W OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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MC74AC377, MC74ACT377
ORDERING INFORMATION
Device MC74AC377N MC74AC377NG MC74ACT377N MC74ACT377NG MC74AC377DW MC74AC377DWG MC74AC377DWR2 MC74AC377DWR2G MC74ACT377DW MC74ACT377DWG MC74ACT377DWR2 MC74ACT377DWR2G MC74AC377DT MC74AC377DTG MC74AC377DTR2 MC74AC377DTR2G MC74ACT377MEL MC74ACT377MELG Package PDIP-20 PDIP-20 (Pb-Free) PDIP-20 PDIP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 75 Units / Rail 1000 / Tape & Reel 38 Units / Rail 1000 / Tape & Reel 38 Units / Rail 18 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb-Free.
MARKING DIAGRAMS
PDIP-20 20 20 MC74ACT377N AWLYYWWG 1 1 20 20 MC74AC377N AWLYYWWG 1 1 1 AC377 AWLYYWWG 1 ACT377 AWLYYWWG SOIC-20W 20 ACT 377 ALYWG G 1 TSSOP-20 SOEIAJ-20
20 74ACT377 AWLYWWG
20 AC 377 ALYWG G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
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MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20W DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE C
K REF
M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 --- --- 0.047 C 1.20 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC -W- H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
20X
2X
L/2
20
11
J J1 B -U- N
L
PIN 1 IDENT 1 10
0.15 (0.006) T U
S
A -V-
N F DETAIL E
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
16X
0.36
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74AC377/D

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